
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:49:09 03/10/2012
-- Design Name:   RA
-- Module Name:   C:/Xilinx92i/PROJECTAIC/tb_RA.vhd
-- Project Name:  Procesador
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RA
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_arith.all;

ENTITY tb_RA_vhd IS
END tb_RA_vhd;

ARCHITECTURE behavior OF tb_RA_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT RA
	PORT(
		inst_word_i : IN std_logic_vector(17 downto 0);
		clk : IN std_logic;          
		ir_out : OUT std_logic_vector(17 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL inst_word_i :  std_logic_vector(17 downto 0) := (others=>'0');

	--Outputs
	SIGNAL ir_out :  std_logic_vector(17 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: RA PORT MAP(
		ir_out => ir_out,
		inst_word_i => inst_word_i,
		clk => clk
	);

	clk <= not clk after 25 ns; --50 ns de periodo

	tb : PROCESS
	BEGIN

		wait for 49 ns;
		inst_word_i <= conv_std_logic_vector(15,18);		
		wait for 50 ns;
		
		assert(ir_out = conv_std_logic_vector(15,18))
						report "ERROR 1 en carga de RA "
						severity FAILURE;
		
		
		inst_word_i <= conv_std_logic_vector(1023,18);
		
		wait for 50 ns;
		assert(ir_out = conv_std_logic_vector(1023,18))
						report "ERROR 2 en carga de RA "
						severity FAILURE;
						
		report ("**********TESTS DE RA SUPERADOS**********")
		severity NOTE;
		
		wait; -- will wait forever
	END PROCESS;

END;
